When designing integrated circuits, the circuit designer must continually consider both efficient space utilization and process capabilities. Such considerations are particularly important when designing around gate conductors. Failure to create area-efficient designs will result in designs that do not meet size specifications. Perhaps worse, failure to create designs within the process capabilities of the fabrication technology will result in ongoing yield issues that may only be capable of being corrected by expensive and time-consuming redesigns.
Modern integrated circuits frequently contain devices wherein gate conductors are electrically connected to diffusion regions formed in a substrate. For instance, it is often desirable in metal-oxide-semiconductor (MOS) capacitors and diodes to connect a gate conductor to a source or drain region of the same or an adjacent MOS device. In order to form such devices, the designer will typically contact the gate conductor through one or more vertical contacts and then tie the gate conductor to the desired diffusion region by use of one or more metal interconnects. FIG. 1 shows an illustrative layout of such a conventional device. Gate conductor 100 is formed at least partially between source and drain diffusion regions 110, 120. Metal interconnect 130 is electrically connected to gate conductor 100 via a vertical contact 140. Metal interconnect 130 is, in turn, electrically connected to the diffusion region 120 by a plurality of vertical contacts 150.
Contacting discrete, unenlarged gate conductors with vertical contacts becomes increasingly more difficult as integrated circuits are reduced in size. Typically, a design that uses such features pushes the limits of process capabilities such as gate conductor dimension control, vertical contact dimension control, and lithographic overlay control. Inadequate control may result in vertical contacts that partially or fully miss landing on a corresponding gate conductor. A possible solution to this process problem, designing gate conductors with pads to act as enlarged landing regions for vertical contacts, utilizes significant additional area in the integrated circuit and is, thus, undesirable.
Moreover, in certain applications, it is beneficial to connect the gate conductor of one device to the gate conduction of one or more other devices. These designs may interconnect the gate conductors in parallel or in series. For example, a common device connects two or more gate conductors in series and uses the interconnected gate conductors to modulate current between shared source and drain regions. Such a device is typically used to reduce hot carrier degradation by reducing the voltage drop between source and drain across any one transistor.
FIG. 2 shows a typical MOS device employing an interconnected gate arrangement. Gate conductors 200 and 210 are formed with source region 230 and drain region 240. A shared diffusion region 250 is formed between the gate conductors 200, 210 of the same conductivity type as the source and drain regions. Gate-level interconnect feature 220 serves to electrically connect gate conductors 200, 210 to each other. Unfortunately, such a design may not be efficient in terms of space utilization. A gate-level interconnect feature, like that shown in FIG. 2, is typically formed outside the active diffusion regions of the device. As a result, its use requires that the gate conductors be extended into this non-active region. Consequently, such a design for interconnecting gate conductors may consume large areas on the integrated circuit and is, thus, undesirable.
There is a need, therefore, for a design and/or method whereby a gate conductor can be electrically connected to a local diffusion region without the need for vertical contacts on the gate structure. In addition, there is also a need for a design and/or method in which a gate conductor can be electrically connected to another gate conductor without the use of gate-level interconnect features like that shown in FIG. 2.